AMD First debut Verano Xielong processor: planned to be launched in 2027, supporting LPDDR5X
The Block
1h ago
Ai Focus
AMD made its debut at the 2026 OCP Global Summit, showcasing the next generation of Verano series EPYC data center processors for the first time. These processors are scheduled to be launched in 2027 and will adopt the Zen 6-core architecture. For the first time, they will also support LPDDR5X memory in the EPYC product line. Su Zifeng stated that these products will be targeted at AI accelerator host nodes and will be used in conjunction with future generations of Instinct GPU.
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News from the IT family on October 13th: AMD officially unveiled its next-generation EPYC series of data center processors for the first time at the 2026 OCP Global Summit, which commenced on October 12th local time.

This series of processors is scheduled to be launched in 2027 and will adopt the Zen architecture. For the first time, it will support LPDDR5X memory in the EPYC product line, providing edge-side computing capabilities for data centers oriented towards AI agents through SOCAMM2 memory modules.

In his keynote speech, AMD CEO referred to Verano as the next step in CPU product layout for the AI era. This processor is mainly aimed at AI accelerator host nodes and is planned to be used in conjunction with future generations of AMD Instinct GPU to meet the computational and memory system requirements of AI agent workloads.

In terms of memory, Verano will adopt a solution that combines LPDDR5X and SOCAMM2 modules. AMD states that SOCAMM2 is a modular memory specification designed for server environments, which is replaceable and easy to maintain, while also taking into account the low power consumption and high bandwidth characteristics of LPDDR5X. AMD believes that this approach will help to improve the performance-to-power ratio of AI data centers and provide more space for rack-level system design.

ComputerBase reports that the Verano processor showcased at the OCP summit by AMD features a configuration with up to 192 cores. However, AMD previous official documents have not confirmed this number of cores, so this parameter should still be subject to the complete specifications to be released later by AMD.

Tom previously reported that the maximum number of related configurations for Verano was 72, with 6 cores and equipped with a 24-channel LPDDR5X memory subsystem; there are currently differences between these two statements.

In terms of interconnection, Verano can provide a connection speed of up to 112 Gbps xGMI, which is used to connect the Instinct MI500 series GPU. However, the final number of cores, interconnection specifications, and complete product configuration are still subject to further disclosure by the official.

Su Zifeng also stated in her speech that by 2030, the market scale of CPU is expected to exceed $200 billion (Note from IT: the current exchange rate is approximately 1.34 trillion yuan), with an annual compound growth rate of about 50% in the coming years. She linked this growth forecast to the development of the workload of intelligent agents AI, believing that related applications will further increase the demand for computing resources from servers CPU.

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