IT News on October 16th: Technology media TechNews reported yesterday (October 15th) that during TSMC's third fiscal quarter (July 2026 to September 2026) earnings conference call, Chairman and CEO Terry Gou announced that they had achieved mass production of advanced packaging with a 5-times larger mask size, and the yield rate was "very excellent." He stated that, for now, no other company besides TSMC is capable of achieving this level, and customers are very satisfied with the mass production results.

IT Note: "Mask size" can be simply understood as the unit of area that can be covered by a single exposure in chip manufacturing. AI Chips, especially high-performance computing chips, are increasingly dependent on packaging multiple computing chips and high-bandwidth memory on the same large substrate. Therefore, the larger the packaging area, the higher the computational power, memory capacity, and interconnection density that can be accommodated, but it also becomes more difficult to ensure a high yield rate.

Wei Zhejia stated that TSMC is developing packaging with a 9x mask size and is moving towards a 14x mask size. Technology media Anue reported in August this year that TSMC's 5.5x mask size CoWoS has entered the high-volume production phase, with the yield of products for multiple AI customers stabilizing at over 98%, and some even reaching 99%. The company plans to expand to mask sizes of over 14x by 2029.

In the face of competitive solutions from Intel EMIB and others, Wei Zhijia did not directly mention their names, but he made it clear that if customers cannot obtain sufficient advanced packaging capacity from their competitors, TSMC will be prepared. He emphasized that TSMC's top priority is to ensure the smooth launch of customers' products, for which it is necessary to provide the best technology and guarantee adequate production capacity.